摘要
本文提出了采用IC芯片PLA元件构成一位、二位全加法功能单元网络[3→2],[2,3→3],并以此基本功能单元组成快速并行全加器和快速乘法器。在介绍设计原理的基础上,给出了具体的逻辑设计和结构框图,并对这些职能部件进行了一点性能分析。
A scheme for arithmetic circuits using one-bit and two-bit full addition cell [3 2], [2, 3 3], constructed by the PLA chips, is investigated. Fast parallel full adder and multiplier are given by means of two logical design block diagram. On the basis of introducing the principle of construction, the performance of the types of the circuits are analysed.
出处
《计算机学报》
EI
CSCD
北大核心
1990年第7期507-515,共9页
Chinese Journal of Computers
