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一种高转换速率衬底电位选择电路的设计 被引量:2

The Design of A Substrate Voltage Select Circuit with High Slew Rate
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摘要 本文基于0.5μm 5V DPTM CMOS工艺设计了一款用于LED驱动芯片的衬底电位选择电路。该电路采用峰值电流镜作为偏置,使其在低电压下能够正常工作,并运用源端输入带正反馈的比较器,使得电路具有一定的迟滞和高的转换速率,最后巧妙的设计了输出级,使输出结果尽可能的与芯片中的最高电压相等。仿真结果显示,比较器的转换速率为55.7V/μs,并且具有0.2V的迟滞,满足设计要求。 Based on the 0.5 μ m 5V DPTM CMOS process, a substrate voltage select circuit for LED driver chip is presented in this paper. The proposed circuit,which based on peak current mirror and source input comparator with forward feedback, makes the circuit can operate under low voltage and has a high slew rate besides a definite hysteresis. In order to the output matches to the maximal voltage in the chip, a special output stage is designed. The simulation results of comparator show that a slew rate of 55.7V/μs and a hysteresis of 0.2V is achieved .
出处 《中国集成电路》 2008年第12期40-43,51,共5页 China lntegrated Circuit
关键词 衬底电位选择 峰值电流镜 高转换速率 迟滞 Substrate Voltage Select Peak Current Mirror High Slew Rate Hysteresis
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参考文献4

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同被引文献15

  • 1Behzad Razavi.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2002.314.
  • 2Zhuo W, Li X, Shekhar S, et al. A capacitor cross-cou- pled common-gate low-noise amplifier[J]. IEEE Trans- actions on Circuits and Systems Ⅱ: Express Briefs, 2005,52 (12) :875-879.
  • 3Eiji Shirai. CMOS multistage preamplifier design for high-speed and high-resolution comparators[J]. IEEE Transactions on Circuits and Systems Ⅱ: Analog and Digital Signal Processing, 2007,54(2) : 166-170.
  • 4Huang Minghsin, Fan Pochin, Chen Kehorng. Low-rip- ple and dual-phase charge pump circuit regulated by switched-capacitor-based bandgap reference[J]. IEEE Transactions on Power Electronics, 2009,24 (5) : 58-63.
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  • 7Luo P, Luo L Y, Li Z J, et al. Skip cycle modulation in switching DC-DC converter [C]//IEEE 2002 Intema- tional Conference on Communications, Circuits and Systems and West Sino Expositions, 2002: 1716-1719.
  • 8AllenPE,HolbergDR.CMOS模拟集成电路设计[M].冯军,李智群,译.2版.北京:电子工业出版社,2012:359-386.
  • 9毕查德·拉扎维.模拟CMOS集成电路设计[M].陈贵灿,程军,张瑞智,等,译.西安:西安交通大学出版社,2002:309-327.
  • 10小林芳直.数字逻辑电路的ASIC设计[M].蒋民,译.北京:科学出版社,2004:33-51.

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