摘要
在数字逻辑电路设计中,常常遇到一些对时钟分频的需求。本文实现了一种基于FPGA的软件化的分频方法,通过对不同的Verilog HDL语言程序语句进行比较分析和仿真综合。
Due go the limitation of the frequency dividers recently widely used, in this paper, a new software method of frequency dividers based on FPGA is introduced. Comparison and analysis are presented, and synthesis and simulation are performed by different Verilog HDL language program statement.
出处
《科技广场》
2008年第10期215-216,共2页
Science Mosaic
