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Register Allocation Algorithm for High-Level Circuit Synthesis for Improved Testability 被引量:1

Register Allocation Algorithm for High-Level Circuit Synthesis for Improved Testability
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摘要 Register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an improved register allocation algorithm that improves the testability called weighted graph-based balanced register allocation for high-level circuit synthesis. The controllability and observability of the registers and the self-loop elimination are analyzed to form a weighted conflict graph, where the weight of the edge between two nodes denotes the tendency of the two variables to share the same register. Then the modified desaturation algorithm is used to dynamically modify the weights to obtain a final balanced register allocation which improves the testability of the synthesized circuits a higher fault coverage than other algorithms with Tests on some benchmarks show that the algorithm gives less area overhead and even less time delay. Register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an improved register allocation algorithm that improves the testability called weighted graph-based balanced register allocation for high-level circuit synthesis. The controllability and observability of the registers and the self-loop elimination are analyzed to form a weighted conflict graph, where the weight of the edge between two nodes denotes the tendency of the two variables to share the same register. Then the modified desaturation algorithm is used to dynamically modify the weights to obtain a final balanced register allocation which improves the testability of the synthesized circuits a higher fault coverage than other algorithms with Tests on some benchmarks show that the algorithm gives less area overhead and even less time delay.
出处 《Tsinghua Science and Technology》 SCIE EI CAS 2008年第6期836-842,共7页 清华大学学报(自然科学版(英文版)
基金 Supported by the National Key Basic Research and Development(973) Program of China (No. 2005CB321604) the National Natural Science Foundation of China (No. 60633060)
关键词 high-level synthesis (HLS) register allocation TESTABILITY weighted graph high-level synthesis (HLS) register allocation testability weighted graph
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参考文献12

  • 1李晓维,张英相,等.High Level Synthesis for Loop-Based BIST[J].Journal of Computer Science & Technology,2000,15(4):338-345. 被引量:1
  • 2Joan E. Carletta,Christos A. Papachristou.Behavioral Testability Insertion for Datapath/Controller Circuits[J].Journal of Electronic Testing.1997(1)
  • 3Harmanani H,Hajar A.An incremental approach for test scheduling and synthesis using genetic algorithms[].Proceedings of thend Annual IEEE Northeast Workshop on Circuits and Systems.2004
  • 4Li Li,Wei Shaojun,Yang Zhilian.Register assignment al-gorithm targeting automatic test pattern generation[].Journal of Tsinghua University(Science and Technology).2001
  • 5Kurdahi F J,Parker A C.REAL:A program for register allocation[].Proceedings of the th Design Automation Conference.1987
  • 6Paulin P G,Knight J P,Girczyc E F.HAL:A multi-paradigm approach to automatic data path synthesis[].Proceedings of the Design Automation Conference.1989
  • 7X. Li,Paul Y,S. Cheung.“High Level Synthesis for Loop-Based BIST”[].Journal of Computer Science and Technology.2000
  • 8Safari S,Jahangir A H,Esmaeilzadeh H.A parameter-ized graph-based framework for high-level test synthesis[].Integration-the Vlsi Journal.2006
  • 9Paulin P G,Knight J P.Force-directed scheduling for the behavioral synthesis of ASIC’s.IEEE Trans[].Computer Aided Design.1989
  • 10Brelaz D.New methods to color vertices of a graph[].Communications of the ACM.1979

二级参考文献4

  • 1Li X,Proc. IEEE 1999 Asianand South Pacific Design Automation Conf. (ASP-DAC’99),1999年,275页
  • 2Li X,Proc IEEE Instrumentation and Measurement Conference(IMTC/99),1999年,2卷,844页
  • 3Lai K,Proc. Int. Conf. Computer Aided Design & Computer Graphics,1997年,460页
  • 4Wang L T,Proc. IEEE Int.Symposium on Cirouits & Systems (ISCAS’96),1996年,1054页

同被引文献12

  • 1王磊,魏少军.优化寄存器需求的资源约束调度算法[J].计算机辅助设计与图形学学报,2004,16(9):1220-1224. 被引量:1
  • 2Bhatia S,Jha N K.Genesis:a behavioral synthesis system for hierarchical testability[C]//Proceedings of IEEE European Design and Test Conference.Los Alamitos:IEEE Computer Society Press,1994:272-276.
  • 3Mujumdar A,Jain R,Saluja K.Behavioral synthesis of testable designs[C]//Proceedings of the 24th International Symposium on Fault-Tolerant Computing.Piscataway:IEEE Computer Society Press,1994:436-445.
  • 4Mujumdar A,Jain R,Saluja K.Incorporating performance and testability constraints during binding in high-level synthesis[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1996,15(10):1212-1225.
  • 5Paulin P G,Knight J P,Girczyc E F.HAL:a multi-paradigm approach to automatic data path synthesis[C]//Proceedings of Annual ACM IEEE Design Automatic Conference.Piscataway:IEEE Computer Society Press,1988:587-594.
  • 6Springer D L,Thomas D E.Exploiting the special structure of conflict and compatibility graphs in high-level synthesis[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1994,13(7):843-856.
  • 7Avra L.Allocation and assignment in high-level synthesis for self-testable data paths[C]//Proceedings of International Test Conference.Piscataway:IEEE Computer Society Press,1991:463-472.
  • 8Li L,Wei S J,Yang Z L.Resource allocation in high-level synthesis with the reduction of hard-to-test structure[J].Chinese Journal of Electronics,2000,9(4):369-374.
  • 9Safari S,Jahangir A H,Esmaeilzadeh H.A parameterized graph-based framework for high-level test synthesis[J].Integration,the VLSI Journal,2006,39(4):363-381.
  • 10Lee T C,Wolf W F,Jha N K.Behavioral synthesis for easy testability in data path allocation[C]//Proceedings of IEEE//ACM International Conference on Computer-Aided Design.Piscataway:IEEE Computer Society Press,1992:616-619.

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