摘要
对LDPC编译码技术进行了介绍,指出LDPC译码算法可以用高度并行的结构实现,可以达到很高的译码吞吐量。提出了分层修正最小和译码算法并对该算法进行了定点仿真,仿真结果表明,该算法性能优良并且能降低迭代次数以提高吞吐量,该算法在最好情况下可以节省一半的迭代次数。设计了一种新的LDPC译码器并完成了FPGA硬件实现,这种译码器能够实现LDPC码高速译码,实现了100 Mbps的译码吞吐量。该译码器能够支持多种通信标准的LDPC码译码,从而节省系统总体成本。
The technique of LDPC is introduced and this paper shows that LDPC decoder can be implemented with highly parallel structure and attain high speed decoding. And a new layered revised min-sum decoding algorithm is proposed, then fixed-point simulation result shows that this algorithm can improve decoding throughout and reduce iteration. Fixed-point simulation result shows that half of iterations can he saved at best condition. And then a new LDPC decoder is designed and hardware implementation with FPGA is completed, this decoder can support high speed decoding and 100 Mbps decoding throughput is fulfilled. Furthermore, it can support several communication standards, so it can save cost.
出处
《系统工程与电子技术》
EI
CSCD
北大核心
2008年第10期2031-2034,F0003,共5页
Systems Engineering and Electronics
基金
国家"863"高技术计划基金资助课题(2006A01Z271)
