摘要
循环冗余校验(CRC)码是数据通信中广泛应用的一种差错检测码。在介绍CRC原理的基础上,以常见的CRC-16为例,用VerilogHDL硬件描述语言设计该算法。利用Altera公司的EDA开发工具软件QuartusII6.0,给出仿真波形图以及可以共享的模块,该模块既是CRC码生成器,又是待校验数据的校验器。仿真结果表明,这是一种实现CRC算法的有效方法,其工作频率可达到420.17MHz。
Cyclic Redundancy Check（CRC） is an error_detection code widely used in the digital communication. Based on the principle of CRC, taking the ordinary CRC-16 as an example, the CRC algorithm is designed by the hardware description language Verilog HDL. The simulation waveform and the encode module for share are also given under Quartus II 6.0, an EDA tool developed by Altera Company. The module is not only the generator of CRC but also the checker of data waiting for checking. The simulation has shown that the method is effective, and it＇s working frequency is up to 420.17 MHz.
出处
《信息与电子工程》
2008年第5期394-396,400,共4页
information and electronic engineering
