摘要
论文讨论的是基于VHDL实现在系统编程平衡GOLD码逻辑电路设计,给出周期与相位可编程平衡GOLD码生成电路设计方案。该方案由最长线性移位寄存器与可选反馈支路构成。在此基础上,论文给出了可实现GOLD码码长在511、1023与2047间可编程变化的设计实例及其VHDL代码,经QuartusⅡ6.0编译与仿真后,结果表明采用文中所述的设计方案是可行的。
This paper discusses the implementation of In the System Programming Balance GOLD code circuit design based on VHDL, and gives out a project design which cycle and phase can be programmable. It is composed of the longest linear feedback shift register and the necessary reactive circuit. Based on this, we gives an example of programmable GOLD code and its VHDL. Its period can be changed in the range of 511,1023 and 2047. The VHDL procedures is compiled and simulated by Quartus Ⅱ 6.0, the results show that this design is feasible in this paper.
出处
《微计算机信息》
北大核心
2008年第29期278-279,283,共3页
Control & Automation
