摘要
基于IEEE 802.16d协议物理层标准中的OFDM模式,设计了一个接收机ASIC。整个接收机设计通过算法和结构优化,采用模块复用和流水线技术,使得接收机结构更加紧凑,运算效率更高,节省了芯片面积。另外,在实现过程中,还采用了低功耗设计技术,以满足终端对低功耗的要求。详细描述了该ASIC接收机的VLSI实现和具体优化过程,对关键算法的性能和实现复杂度进行了权衡分析。该ASIC接收机经过综合后面积为3.481 mm2,在64 QAM调制方式下,可支持最大数据速率达30 Mb/s,适合户外多径情况下的固定接入无线分组通信。
An OFDM receiver ASIC specifically targeting IEEE 802. 16d standard was designed and fabricated. By algorithms and structure optimization and extensive use of time-sharing and pipeline, the receiver achieved higher computation efficiency with a compact structure and smaller silicon area. VLSI implementation and optimization of the ASIC was described. Finite-precision effects were investigated to minimize the computation requirements for major signal processing blocks. Performance and implementation cost tradeoff on key algorithms was also analyzed. The synthesized receiver ASIC occupies a silicon area of 3. 481 mm^2 , and it could provide a maximum data-rate of 30 Mb/s in 64 QAM modulation mode, which is suitable for packet-based fixed access applications.
出处
《微电子学》
CAS
CSCD
北大核心
2008年第4期562-568,共7页
Microelectronics
基金
国家自然科学基金资助项目(60425413)