摘要
提出了一种以任意字宽度对ＳＤＨ帧同步信号扰码／解扰的并行机制，解决了串行帧同步扰码器不适于高速信号处理的问题，并易于采用现场可编程门阵列ＦＰＧＡ实现．
A parallelism architecture of the frame synchronous scrambler and descrambler with an arbitrary word width performed on the Synchronous Digital Hierarchy (SDH) frame is presented, which solves the problem encountered in using the serial frame synchronous scrambler and descrambler at a high data rate. It is shown that it is easy to implement the mechanism using the Field Programmable Gate Array (FPGA).
出处
《西安电子科技大学学报》
EI
CAS
CSCD
北大核心
1997年第3期342-345,共4页
Journal of Xidian University
关键词
同步数字序列
SDH网
扰码器
解码器
synchronous digital hierarchy (SDH) parallel frame synchronous scrambler and descrambler field programmable gate array
