摘要
论述了2μmCMOS门阵列技术，特别着重介绍了门阵库、库单元和母片的建立，同时对门阵列布局布线流程进行了探讨。
This paper describes the design technology for 2μm CMOS gate array including masterslice and cells, architecture, auto placement and routing 9 and verification. Authors use Cadence design topl to complete design process.
出处
《微处理机》
1997年第1期11-15,共5页
Microprocessors
