摘要
介绍了一种新型低抖动快速锁定时钟稳定电路。该电路通过检测输入时钟信号的上升沿,产生一个尖峰脉冲和一个精确延迟半个周期的尖峰脉冲,共同组成一个稳定的低抖动时钟。该电路采用0.35μm标准CMOS工艺库,在Cadence环境下进行仿真,在100 MHz输入时钟频率下,输出时钟抖动为56 fs,电路的功耗仅有35 mW。
A novel low-jitter fast-locking clock stabilizer is presented. By detecting the rising edge of the input clock signal, the circuit generates two peak pulses, one of which is exactly delayed by half cycle, to form a stable clock with low jitter. The circuit was simulated based on 0.35μm standard CMOS technology. At input clock rate of 100 MSPS, the circuit has a peak-to-peak clock jitter of 56 fs, and its power dissipation is only 0. 35 mW.
出处
《微电子学》
CAS
CSCD
北大核心
2008年第1期137-140,共4页
Microelectronics
