摘要
提出和分析了一种８ＤＰＳＫ解调器中全数字判决反馈时钟定时和载波相位同步器，该同步器误差检测的自噪声小，同步跟踪速度快，抖动小．文中分析了误差检测曲线及平均捕获时间等，并经计算机模拟．该同步器与解调器一起在ＤＳＰ芯片ＴＭＳ３２０Ｃ２５上实现．给出了模拟和测试结果．
A new all digital decision directed clock timing and carrier phase synchronizer in 8DPSK demodulator is proposed and analyzed. It's error detection self noise is small, the synchronization tracking speed is high, and the tracker jitter variance is small. The error detection curves and mean acquisition time are analyzed and checked with simulation. The synchronizer was implemented, together with the 8DPSK demodulator, on a TMS320C25 DSP. The results of simulation and test are given.
出处
《东南大学学报（自然科学版）》
EI
CAS
CSCD
1997年第5期102-108,共7页
Journal of Southeast University：Natural Science Edition
基金
邮电部"移动无线数据通信系统"项目资助
