摘要
阐述了Ku波段低相噪锁相频率源的研制过程。在低输入参考频率10 MHz的情况下,输出高达11.8 GHz的点频信号,倍频恶化达到61 dB,如何实现从10 Hz^1 MHz频偏范围内各点的相位噪声指标要求是需要攻克的技术难题。具有超低相噪基底的模拟鉴频鉴相器件HMC440的应用为该项目的成功研制奠定了坚实的基础。
This paper introduces a design of Ku- band Phase- Locked Loop （PLL） frequency synthesizer with low phase noise. The PI.L generates a high single frequency of 11.8 GHz related to a low crystal reference frequency 10 MHz input. According to the theory of frequency multiplier we can compute the depravation of phase noise is almost 61 dB. For this reason, how to obtain low phase noise at all offsets from 10 Hz to 1 MHz is a big problem. The application of HMC440 which is an ultra low phase noise floor phase frequency detector produced by Hittite makes the subject to be successful accomplished.
出处
《现代电子技术》
2007年第23期85-87,共3页
Modern Electronics Technique
关键词
鉴频鉴相器
相位噪声
锁相频率合成器
杂散抑制
phase frequency detector
phase noise
PLL frequency synthesizer
spur restraint
