摘要
提出了H.264/AVC硬件编码器的一种3级流水结构,以此来提高硬件加速电路的处理能力和利用效率。鉴于H.264编码芯片验证的复杂性,还提出了一种基于ADSP-BF537的新型多媒体SoC验证平台,并讨论了如何利用BF537,对H.264编码芯片进行全面、高效的软硬件协同验证。
To improving the process capabilities and utilized efficiency of the hardware accelerator, 3 pipeline architecture for H.264 video encoder is presented. This paper also introduces a novel multimedia SoC verification platform based on ADSP-BF537 since the verification of H.264 encoder chips is so complexity, and finally, How to using BF537 for software/hardware co-verifing the H.264 encoder chip completely and effectively is discussed.
出处
《中国集成电路》
2007年第11期55-59,共5页
China lntegrated Circuit
