摘要
在阐述咬尾卷积码编码器基本工作原理的基础上,提出了基于Verilog HDL语言设计(2,1,6)咬尾卷积码编码器的方法。给出了利用现场可编程门阵列器件设计的咬尾卷积码编码器电路,并进行了编译和波形仿真,综合后下戢到FPGA芯片StratixⅡGX:EP2SGX90FF1508C3中,测试结果表明该编码器具有实际的使用价值,更重要的是提高了无线通信系统的数据传输质量。
This paper discusses the encoding principles of the convoluti designing the （2, 1, 6） tail_biting CC convolution encoder using Verilog on code, and presents a method for HDL language. The circuit of the tail_biting CC is designed by FPGA, which is then compiled and wave simulated. Finally, it is downloaded af- ter synthesis to the Stratix II GX： EP2SGX90FF1508C3. Test results indicate that this encoder is of practical value, and able to improve the quality of data in the wireless communication system.
出处
《电子科技》
2007年第11期55-58,共4页
Electronic Science and Technology
