摘要
针对用FPGA实现的高速自适应滤波器与高速ADC数据处理速度不匹配、容易产生串扰等问题,提出了一种基于异步FIFO技术的高速采样自适应滤波系统方案,选用双通道高速AD9238-40作为前置输入级,用片内异步FIFO作高速缓存,用FPGA控制采样与滤波,给出了系统的结构框图,对异步FIFO与采样滤波控制器进行了仿真,并将异步FIFO与采样滤波控制器集成在同一FPGA上,完成了对双通道高速AD9238与自适应滤波器的高速匹配控制。仿真结果表明:该方案既能降低系统的成本,又能有效降低高频可能引起的干扰,对于高速实时电路处理具有一定的参考意义。
Aiming at the high-speed matching controlling problems between adaptive filters inplemented by FPGA and the high-speed AD converters, a high-speed sampling and adaptive filtering system was designedusing asynchronous FIFO. The dual channels AD converter AD9238-40 was used as input stage, two asynchronous FIFOs on-chip were used as high-speed buffer memory, and the sampling and adaptive filtering was controlled by FPGA. The asynchronous FIFO was customized and simulated on Quartus Ⅱ, the sampling and adaptive filtering controller was designed and also simulated on Quartus II. The highspeed matching controlling of the dual channels AD converter AD9238-40 and the adaptive filter was implemented. At last, the schematic diagram of the hardware system was also given. The sampling and filtering controller and the asynchronous FIFOs was integrated on a chip, it could reduce interfere may caused by high frequency and the cost of the system.
出处
《电测与仪表》
北大核心
2007年第8期60-62,66,共4页
Electrical Measurement & Instrumentation
关键词
异步FIFO
高速采样
自适应滤波器
自适应滤波系统
asynchronous FIFO
high-speed system sampling
adaptive filter
adaptive filtering system
