摘要
本文设计了适用于SOC(System On Chip)的快速乘法器内核。通过增加一位符号位,可以支持24×24无符号和有符号乘法。在乘法器的设计中,采用了改进的Booth算法来减少部分积的数目,用压缩的Wallace Tree结构将产生的部分积相加以减少关键路径的延时。该电路通过Hspice仿真最大延迟达到9.32ns,从而获得较高的速度和性能。
This paper describes a 24×24 Multiplier which is used for SOC（ System On Chip）. The multiplier supports both signed and unsigned integer multiplication by a additional sign bit.Designing use Wallace tree composed to add up Partial-product in order to reduce the critical path delay. This ALU unit delays not to go beyond 9.32ns by means of Hspice simulating.so it has the higher speed and function.
出处
《微计算机信息》
北大核心
2007年第04Z期155-156,136,共3页
Control & Automation
基金
安徽省2005自然科学基金(050420202)
