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CAN总线位定时与同步机制的研究 被引量:10

Research on CAN Bit Timing and Synchronization Mechanism
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摘要 在CAN规范中,位定时和同步机制是既重要又难于理解的环节之一,它不仅关系到对规范其它相关内容的理解,甚至对节点开发的成功与否产生直接的影响.文中介绍了位时间(周期)的组成与结构,总结并归纳了位定时的作用;在此基础上,给出了硬同步和重同步的定义,重点分析了硬同步和重同步的机理,并给出了它们相应的图解,形象而又清晰地表明了其本质;以独立CAN控制器为例,详细说明了在一般开发和工程实际中,位定时参数设置和计算的一般方法及步骤. Bit timing and synchronization mechanism is one of a important and hard understanding link in CAN specification, it is not only referred to the understanding of other correlative content, but also has direct influence to the successful node development. The composition and structure of Bit time(period) are introduced, the function of bit timing is generalized ;based on this, the definition of hard synchronization and resynchronization are provided, the mechanism of synchronization and resynchronization are analyzed, moreover, the corresponding figures are also provided, and it is clearly present its essence. Take stand-alone CAN controller as an example, the general method and procedure of bit timing parameter setting and calculation in universal development and project practice are illustrated in detail.
出处 《电子器件》 CAS 2007年第4期1499-1502,共4页 Chinese Journal of Electron Devices
关键词 位定时 硬同步 重同步 时间份额 参数 bit timing hard synchronization resynchronization time quantum parameter
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参考文献6

  • 1Egon Jhnk,Klaus Dietmayer.Application Note Determination of Bit Timing Parameters for SJA1000 CAN Controller,AN97046,Philips Semiconductors,1997.
  • 2李芳,刘鲁源,吕伟杰.CAN总线位定时和同步机制的分析[J].电子产品世界,2005,12(05A):106-107. 被引量:6
  • 3Dzhelekarski Peter,Volker Zerbe M.SC,et al.FPGA Implementation of Bit Timing Logic of CAN Controller[C]//27th Int'l Spring Seminar on Electronics Technology,Technology University of Sofia,Bulgaria,2004:214-220.
  • 4CAN Specification Version2.0[R].Parts A and B,Philips Semiconductors,1992.
  • 5SJA1000.Stand-alone CAN controller[R].Philips,Product Specification,2000.
  • 6Bruce Emaus.Application Note Basic CAN Bit timing Version1.0[R].AN-AND-1-106,Vector CANtech,2003.

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