摘要
平方根算法是科学计算和工程应用中的基本运算之一,然而由于此算法的复杂性,因此用FPGA很难实现。一般的平方根算法,使用一定量的迭代运算,由传统的加法器和减法器构成,资源占用少,但速度较慢。而在一些实时性要求较高的系统中,对速度的需求比较高。基于此,给出了一种平方根算法,是由高通流水线方式实现,由多路加法器和减法器构成,能够在一个周期内给出结果,相对于传统的平方根算法速度大大增加了。
Square root arithmetic is one of the basic arithmetic, but it is hard to implement on FPGA because of the complexity. Usually, the non - restoring square root algorithm is low - cost iterative implementation which uses a traditional adder/ subtrator. While making better use of the resource,the speed is much slower. In this paper, we present a fast square root based on FPGAs,it is high- throughput pipelined implementation which uses multiple adder/subtractors.
出处
《现代电子技术》
2007年第14期64-65,72,共3页
Modern Electronics Technique
