摘要
新型的现场可编程逻辑门阵列(FPGA)一般采用层次化结构,这种结构有利于提高资源利用率和布通率,与平面结构相比,层次化的设计流程需要进行基本逻辑单元LE的装箱(packing)操作.提出了一种新的FP-GA装箱算法,可以减少装箱后可配置逻辑单元(CLB)外部的线网数,进而达到减少布线所需的通道数.该算法与以前的算法相比,线网数减少25%以上,布线通道数减少9.9%以上.算法的时间复杂度仍然是线性的.
The structure of the new type FPGA is usually hierarchical; this kind of design style improves the resource utilizing ratio and routability. Compared with flatten style, its design flows require LE packing operation included. This paper proposes a new packing algorithm to reduce the number of the inter-cluster wires. Compared with previous algorithms the number of nets has been improved about 30% and the number of muting tracks about 10%. The time eornplexity of this algorithm is still linear.
出处
《复旦学报（自然科学版）》
CAS
CSCD
北大核心
2007年第1期59-64,共6页
Journal of Fudan University：Natural Science
基金
上海市应用材料科技合作共同计划资助项目(AM0406)
