摘要
总结了ＶＬＳＩ版图验证中提取电阻参数的各种方法的优缺点，给出了一种基于边界元法的电阻提取算法．将该算法用于几个实例中。
Methods of parameter extraction in VLSI layout verification are studied and a new resistance extractor based on a boundary element method is presented.The algorithm is used in several examples,and the results show that its effect is satisfactory.
出处
《上海交通大学学报》
EI
CAS
CSCD
北大核心
1997年第3期41-45,共5页
Journal of Shanghai Jiaotong University
基金
"八.五"攻关资助项目
关键词
版图验证
电阻提取
边界元法
大规模集成电路
VLSI layout verification
resistance extraction
boundary element method
