摘要
介绍了用ＦＰＧＡ实现先行进位单元阵列除法器的原理及方法。本除法器在速度上不仅较软件方法快近十倍，而且较传统的硬件除法器有很大的提高；同时，利用ＦＰＧＡ设计技术，将本除法器集成在一单片的ＦＰＧＡ器件上。
The theory and method of precedent cellular arrays divider by means of FPGA are introduced. The divider is not only almost ten times faster than the software method, but also faster than the hardware divider; at the same time, the divider is integrated into one chip by means of FPGA technology. This provides a very effect access to realizing the high speed processing module.
出处
《国防科技大学学报》
EI
CAS
CSCD
1997年第1期66-70,共5页
Journal of National University of Defense Technology
