摘要
设计了应用于低中频GSM接收机的三阶单环单比特结构Σ-Δ A/D转换器。调制器采用全差分开关电容积分器实现。仿真结果显示,在工作电压为3 V、信号带宽200 kHz、0.35μm CMOS工艺的条件下,过采样率选择为64,信号/噪声失真比(SNDR)达到85 dB,功耗不超过11mW。
A third-order single-loop 1-bit ∑-△ A/D converter for low-IF GSM receiver is designed. Based on a 0. 35 μm CMOS technology, and designed with fully differential switched-capacitor integrators, the modulator of the A/D converter operates at a 3-V power supply with an input signal of 200-kHz bandwidth. Simulation results indicate that the third-order single-loop structure has a signal-to-noise distortion ratio （SNDR） of 85 dB and dissipates less than 11 mW of power at an over-sampling ratio of 64.
出处
《微电子学》
CAS
CSCD
北大核心
2007年第1期49-52,共4页
Microelectronics
基金
国家自然科学基金资助项目(90307016)
