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面向CPU芯片的验证技术研究 被引量：10

A Study on CPU Chip-Oriented Verification Technology
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摘要 CPU芯片规模大、复杂度高,在芯片设计的不同阶段进行多层次的验证,保证芯片的正确性非常关键。文章探讨了模拟验证、FPGA仿真、形式验证和静态时序分析等验证方法,提出了一种多级验证体系方法,实现CPU芯片的多层次验证,并成功地验证了自行设计的微处理器的正确性和兼容性。 CPU chip is of large scale and extraordinary complexity. It is very important to perform multilevel verifications in different phases of chip design, in order to ensure the validity of the chip. Verification methods, such as simulation verification, FPGA emulation, formal verification and static timing analysis （STA）, are addressed. A multilevel verification system has been proposed and applied to the verification strategy of CPU chip. This system has been successfully used to verify the validity and compatibility of a self-designed microprocessor.
作者 胡建国 位招勤 张旭 曾献君
机构地区 国防科技大学计算机学院 湖南广播电视大学
出处 《微电子学》 CAS CSCD 北大核心 2007年第1期16-19,23,共5页 Microelectronics
基金 国家自然科学基金重大研究计划资助项目(90207011) 国家高技术研究发展(863)计划资助项目(2002AA110020) 校预研基金资助项目(JC03-06-007)
关键词 CPU 模拟验证 FPGA仿真 形式验证 静态时序分析 多级验证 CPU Simulation verification FPGA emulation Formal verification Static timing analysis Multilevel verification
分类号 TN407 [电子电信—微电子学与固体电子学]
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参考文献6

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二级参考文献30

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共引文献32

同被引文献59

  • 1刘强,王荣生.基于改进的BOOTH编码的高速32×32位并行乘法器设计[J].计算机工程,2005,31(6):200-202. 被引量：4
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引证文献10

二级引证文献12

微电子学
2007年 第1期

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