摘要
帧同步器采用硬件描述语言AHDL设计,基于同步状态机实现帧同步信号的提取,对串行输入数据具有动态搜索、校验、锁定帧同步信号的功能和自适应相位的特点。可用于数字通信系统接收端,实现帧同步信号的提取。为了便于装置的调试与测试,设计中还增加了自检数据源产生逻辑,以实现装置的自检功能。整个设计可集成到一片CPLD或FPGA中,易于参数和程序的修改,适用于多种帧结构,具有很好的可移植性。结果表明,该系统运行稳定,很好地完成了帧同步信号的提取。
The frame synchronizer was designed based on synchronization state machine using a hard description language, AHDL. To serial data, it possesses functions of dynamic search, verification, and lock of synchronization signal, characterized by self-adaptive phase, the device can be used as digital transmission receiver to extract frame synchronization signal. To be convenient for debug and test, the design adds self-test data source generated logic, the device possesses functions of self-test. All circuits can be integrated in one CPLD or FPGA chip, which makes programs and parameters be modified easily, applies to various configurations of frame, makes programs much transplantable. The testing results demonstrate that the system runs steadily and extraction of synchronization signal has been accomplished perfectly.
出处
《电子测量技术》
2007年第2期72-74,77,共4页
Electronic Measurement Technology
基金
北京交通大学"十五"专项科技基金(DXJ05011)资助项目
关键词
数传系统接收端
帧同步器
状态机
AHDL
digital transmission receiver
frame synchronizer
state machine
AHDL
