摘要
提出了一种双精度浮点数字信号处理器Data-RAM的RTL模型设计方法.分析了Data-RAM的结构和访问机制,采用自顶向下的方法和VHDL语言,实现了Data-RAM的RTL模型设计并验证了其功能的正确性.该模型支持3地址独立进行数据存取,支持字节、半字、字的读写访问和双字的读访问.在访问地址不冲突的前提下,最大可以在同一时钟周期进行2次64 bit的读操作和1次32 bit读写操作.Data-RAM的RTL模型设计为门级和物理级的性能设计提供了参考.
A register translation level （RTL） module design method of Data-RAM for double precision float-point digital signal processor is proposed. Structure and accessing principles of Data-RAM are studied. By using top down method and VHDL, RTL module is designed and the correctness of function confirmed. This RTL module supports access in three addresses independently. The access modes include byte, half word, word, double word. Two 64 bit data can be read and one 32 bit data can be written or read in one clock cycle, if accesses do not conflict. The design of Data-RAM on gates level and physical level can be directed by this RTL module.
出处
《北京理工大学学报》
EI
CAS
CSCD
北大核心
2007年第1期68-72,共5页
Transactions of Beijing Institute of Technology
基金
国家部委预研项目(200205)
