摘要
提出了一种基于方块超前进位的快速进位跳跃加法器。该加法器的跳跃方块采用不等尺寸的二级方块超前进位逻辑,其可变的方块尺寸缩小了关键路径的延时,而方块内部的快速超前进位逻辑使得延时进一步减小。除第一个方块以外,其他每个方块进位仅有两级门延时。该进位跳跃加法器已用PSp ice仿真工具进行了功能验证和仿真。门级延时和PSp ice仿真分析表明,所提出的进位跳跃加法器的速度优于通用优化方块分配的进位跳跃加法器。
A fast carry-skip adder is proposed based on variable-sized two-level block carry-lookahead logic. The variable block sizes minimize critical path delay. Within blocks, the fast carry-lookahead logic is used to decrease the delay. When the carry of the first block is generated, each of the other six blocks has only two gate delays. The adder is functionally verified and simulated using PSpice. The analysis of the gate delay and the simulation reveal that the proposed adder can provide the faster speed than the conventional carry-skip adder with the optimal block distribution.
出处
《南京航空航天大学学报》
EI
CAS
CSCD
北大核心
2006年第6期786-790,共5页
Journal of Nanjing University of Aeronautics & Astronautics
