摘要
设计了一种软硬件协同处理的H.264解码器系统方案,基于该方案给出CAVLC解码模块的硬件实现结构,采用有限状态机实现解码的流程控制,并对其查表部分进行优化。验证结果表明,在尽量降低硬件资源损耗的基础上,该方案能满足H.264基本框架4CIF格式图片30f/s(帧/秒)实时解码的要求。
The system design of an H.264 decoder based on the cooperation of software and hardware is presented. With this scheme, the paper describes a hardware architecture of CAVLC decoder module by using finite state machine to control the decoder flow and optimization of code-table search to increase the speed. Simulation results testify that the design can realize real time decoding of bit stream in H.264 baseline profile 4CIF with 30 f/s while minimizing the use of hardware resources.
出处
《电视技术》
北大核心
2006年第12期23-25,84,共4页
Video Engineering
