摘要
在RVM层次化的验证模型中,层与层之间的连接是通过通道来完成的。利用通道结构可以简化验证环境,消除层与层之间的关联性,实现模块之间的即插即用(plugandplay)。最后,通过驱动和处理器之间的通道连接,给出了一个设计实例。
In the RVM layered verification model, the connection between layers is achieved by Channel. By the use of Channel, the verification environment is simplified, relevancy between layers is avoided , and plug and play in module is accomplished. At last, by xactor and driver ,one design channel example is presented.
出处
《国外电子测量技术》
2006年第11期76-79,共4页
Foreign Electronic Measurement Technology
关键词
RVM
通道
SOC
DUT
RVM （ reference verification methodology）, Channel, SOC （system-on-chip）, DUT （ design under test）.
