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基于△V_(GS)权重的CMOS恒压源

CMOS voltage reference based on weighted ΔV_(GS)
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摘要 针对全CMOS结构制作恒压源方法中存在的功耗过大问题,提出了一种利用CMOS亚阈值特性的恒压源制作方案.该电路基于NMOS和PMOS处于饱和区工作时,两者的栅源电压随温度变化权重不同的原理,将其作相关运算,得到温度系数极低的恒压输出.基于MOS管亚阈值特性产生的电路模块中的偏置电流很小,导致功耗仅50 μW.采用中芯国际0.18 μm数模混合工艺制造了该电压源结构,测试结果显示,在21～110 ℃的温度范围内,电路的温度系数达到了2.5×10^-5/℃.当电源电压达到1.4 V以上时,电路就可以正常工作,且其电源电压抑止比为-57 dB. The power consumption in CMOS voltage references is often excessive. This paper describes a voltage reference based on the CMOS sub-threshold characteristics that requires less power. By using the weighted difference between the gate-source voltages of an NMOS and a PMOS operating in the saturation region, the resulting output voltage has a very low temperature coefficient and a high power supply rejection ratio since the current supplied to the voltage source is based on the MOSFETs operating in the sub-threshold region. The voltage source was fabricated with the mixed-signal technology of 0.18 μm of semiconductor manufacturing international corporation （SMIC）. Measurements show that the temperature coefficient is only 2.5 × 10^-5/℃ between 21℃ to 110℃. The voltage source works well when VDD is above 1.4 V. The power supply rejection ratio is - 57 dB.
作者 张洵 王鹏 靳东明
机构地区 清华大学微电子学研究所
出处 《清华大学学报（自然科学版）》 EI CAS CSCD 北大核心 2006年第10期1739-1741,共3页 Journal of Tsinghua University(Science and Technology)
关键词 集成电路 恒压源 温度系数 电源电压抑制比 integrated circuit voltage reference temperature coefficient power supply rejection ratio
分类号 TN47 [电子电信—微电子学与固体电子学]
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参考文献13

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清华大学学报（自然科学版）
2006年 第10期

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