期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

高层次综合和布图规划相结合的解空间分析

Searching Space Analysis of Integrating HLS and Floorplan
在线阅读 下载PDF
导出
摘要 针对高层次综合和布图规划互为输入/输出导致的不收敛问题,通过在高层次综合和布图规划的表示法中间构造一座“桥梁”,用一个统一的表示法表示高层次综合和布图规划相结合的搜索空间;在此基础上,对模拟退火算法在该空间上的搜索收敛性进行了分析. In the research of integrating high level synthesis （HLS） and floorplan, the astringency of design space searching algorithms can not be assured because floorplan and HLS are mutual input and output. In this paper, a ＂bridge＂ is constructed between the representation of HLS and floorplan, and the searching space of integrating HLS and floorplan can be represented by a single representation. Based on this new representation, the astringency of simulated annealing algorithm on this design space is analyzed.
作者 王云峰 边计年 周强 洪先龙
机构地区 清华大学计算机科学与技术系
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2006年第10期1478-1483,共6页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金(90207017 90407005) 国家自然科学基金重点项目(60236020) 国家自然科学基金重大国际合作研究(60121120706)
关键词 高层次综合和布图规划相结合 表示法 模拟退火 收敛性分析 integrating high level synthesis and floorplan representation simulated annealing astringency analysis
分类号 TP302.1 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献9

  • 1Micheli Giovanni De.Synthesis and optimization of digital circuits[M].New York:McGraw-Hill,1994:163-166
  • 2Kong Jeong-Taek.CAD for nanometer silicon design challenges and success[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2004,12(11):1132-1147
  • 3Weng J P,Parker A C.3D scheduling high level synthesis with floorplanning[C] //Proceedings of the 28th ACM/IEEE Design Automation Conference,San Francisco,1991:668-673
  • 4Tarafdar Shantanu,Leeser Miriam.A data-centric approach to high-level synthesis[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2000,19(11):1251-1267
  • 5Papa G,Silc J.Using simulated annealing and genetic algorithm in the automated synthesis of digital systems[C] //Proceedings of the 2nd IMACS International Conference on Circuits,Systems and Computers,Piraeus,1998:940-944
  • 6Jang Hyuk-Jae,Pangrle B M.GB:a new grid-based binding approach for high-level synthesis[C] //Proceedings of the 6th International Conference on VLSI Design,Bombay,1993:180-185
  • 7Moshnyaga Vasily G,Tamaru Keikichi.A floorplan based methodology for data-path synthesis of sub-micron ASICs[J].IEICE Transactions of Information and System,1996,E79-D(10):1389-1395
  • 8Hong Xianlong,Huang Gang,Cai Yici,et al.Corner block list:an effective and efficient topological representation of non-slicing floorplan[C] //Proceedings of IEEE/ACM International Conference on Computer Aided Design,San Jose,2000:8-12
  • 9Chung K L.Markov chains with stationary transition probabilities[M].2nd ed.New York:Springer,1967:78-119
计算机辅助设计与图形学学报
2006年 第10期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部