摘要
在诸如信息安全应用领域中,除法运算特别是大数(多个机器字长整数)除法运算速度是制约公钥密码算法运算速度提高的瓶颈。针对公钥密码算法VLSI实现需要,本文在介绍SD数据表示的基础提出了一种新的大数除法算法,并给出了其VLSI实现逻辑结构。实验结果表明,这种除法器的VLSI实现具有很好的性价比。
Division operations, especially very long integer （multi-precision integer） division operations are always the bottleneck of asymmetric key cryptographic calculations. According to the requirements of asymmetric cryptographic algorithms＇ VLSI implementation, this paper presents a novel very long integer division algorithm based on the SD （signed digit） number representation. The implementation logic of the SD division unit is discussed in detail The experimental results show that the SD division unit presented in the paper is highly efficient with good cost-performance trade-off.
出处
《计算机工程与科学》
CSCD
2006年第8期11-13,共3页
Computer Engineering & Science
基金
国家自然科学基金资助项目(60173040)
国家863计划资助项目(2002AA1Z1080)
关键词
SD数据表示
大数除法
公钥密码
SD number representation
very long integer division
asymmetric key cryptography
