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用于CMOS图像传感器的列并行高精度ADC 被引量：4

Design of a High Resolution Column ADC for CMOS Image Sensor
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摘要 设计了一种适用于CMOS图像传感器的列并行Single-slopeADC。采用的列并行ADC,同时对多数据源并行处理,增强了数据吞吐量,特别适用于CMOS图像传感器大像素阵列的数据处理。分析了影响ADC精度的因素,并给出了减小失调的方法。该ADC在0.35μm工艺下成功流片验证,测试结果表明,该ADC,在50MS/s的高数据吞吐量下,实现了CMOS图像传感器的8bit精度的设计要求和17.35mW的低功耗,以及0.62mm2的芯片面积。ADC的DNL=0.8LSB,INL=1.096LSB。 A design of column parallel single-slope ADC for CMOS image sensor is presented. Proposed column ADC deals with multiple data simultaneously, which enhances data throughput and is fit for data process of large pixel array of CMOS image sensor. The factors which incluence the resolution of the ADC are analyzed, and the methods decreasing offsets are given. The ADC is successfully taped out with 0.35 μm process, the testing result shows that, the presented ADC achieves 8-bit resolution in 50 MS/s high speed, which is required by CMOS image sensor, while dissipating 9.5 mW and costing 0.62 mm^2 area. The DNL and INL of the ADC are 0.8LSB and 1. 096LSB respectively.
作者 张娜 姚素英 徐江涛
机构地区 天津大学专用集成电路设计中心
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2006年第3期349-353,共5页 Research & Progress of SSE
基金 国家自然基金资助项目(60576025) 天津市科技发展计划攻关项目(033183911)
关键词 图像传感器 列并行 单斜 模数转换器 image sensor column parallel single slope analog-to-digital converter
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献4

  • 1Mendis Sunetra K.CMOS active pixel image sensors for highly integrated imaging system[J].IEEE Journal of Solid-state Circuits,1997,32(2):187-197.
  • 2Razavi Behzad,Wooley Bruce A.Design techniques for high-speed,high-resolution comparators[J].IEEE Journal of Solid-state Circuits,1992,2 7(12):1 916-1 926.
  • 3Fan X P,Chan P K.A CMOS high-speed multistage preamplifier for comparator design[J].IEEE Circuits and Systems,2004,1:545-548.
  • 4Akira Yukawa.A CMOS 8-bit high-speed A/D converter[J].IEEE Journal of Solid-state Circuits,1985,SC-20(3):775-779.

同被引文献28

  • 1王旭颖.图像传感器CMOS的性能及发展趋势[J].内蒙古民族大学学报（自然科学版）,2013,28(5):502-505. 被引量：3
  • 2钱默抒,熊克.智能微尘[J].电子元件与材料,2005,24(9):32-32. 被引量：4
  • 3Mahmoodi Alireza,Dileepan Joseph.Optimization of delta-sigma ADC for column-level data conversion in CMOS image sensors[C] // Proceeding of IEEE Instrumentation and Measurement Technology Conference.New York:IEEE Press,2007:1-6.
  • 4Furuta Masanori,Nishikawa Yukinari,Inoue Toru,et al.A high-speed,high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters[J].IEEE Journal of Solid-State Circuits,2007,42 (4):766-774.
  • 5Ravindran A,Savia A,Leonard J.Digital error correction and calibration of gain non-linearities in a pipelined ADC[C]//Proceedings of International Symposium on Circuits and Systems.New York:IEEE Press,2004:I-1-I-4.
  • 6Snoeij M F,Theuwissen A J P,Makinwa K A A,et al.Multiple-ramp column-parallel ADC architectures for CMOS image sensors[J].IEEE Journal of Solid-State Circuits,2007,42 (12):2968-2977.
  • 7Snoeij M F,Theuwissen A J P,Huijsing J H.A 1.8 V 3.2/spl mu/W comparator for use in a CMOS imager column-level single-slope ADC[C]//Proceedings of IEEE International Symposium on Circuits and Systems.Kobe,Japan,2005:6162-6165.
  • 8Yukawa Akira.A CMOS 8-bit high-speed A/D converter IC[J].IEEE Journal of Solid-State Circuits,1985,SC-20 (3):775-779.
  • 9Furuta Masanori,Kawahito Shoji,Inoue Toru,et al.A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors[C]// Proceedings of the 31st European Solid-State Circuits Conference.New York:IEEE Press,2005:411-414.
  • 10Kuo Chun-Hsicn,Kuo Tai-Haur.A cyclic A/D conversion technique with improved SFDR[C]// Proceedings of International Symposium on Integrated Circuits.New York:IEEE Press,2007:394-397.

引证文献4

二级引证文献6

固体电子学研究与进展
2006年 第3期

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