摘要
提出了一种组合电路设计错误诊断算法,该算法结合传统基于模拟的方法和可满足性问题求解技术,在不依赖于故障模型的条件下实现对电路逻辑错误的诊断定位.提出了基于布尔可满足性的增量式电路诊断方法,通过对可满足解依据电路结构信息筛选分级,提高了多错误诊断定位的分辨率和准确性;并提出多项启发式方法,避免了大量不必要的操作,使算法在时间和内存上保持有效性.实验结果表明,利用形式验证的技术来导向模拟的过程,抓住了高复杂度的多错误定位问题的特征,提高了电路错误诊断的效率.
A novel design error diagnosis algorithm for combinational circuits is presented. It can perform model-free logic error location by combining traditional simulation-based approach with a SAT solver. An incremental SAT-based diagnosis method is proposed. We improved the resolution and accuracy of diagnosis by ranking and screening sat solutions with structural information of circuits. A number of heuristics are proposed that keep the method＇s memory and run-time efficient. Experimental results show that using formal techniques to direct simulation captures the main characteristics of error location and improves the effectiveness and efficiency of design error diagnosis.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2006年第9期1383-1390,共8页
Journal of Computer-Aided Design & Computer Graphics
基金
国家自然科学基金(90207002)
关键词
设计错误诊断
布尔可满足性
电子设计自动化
design error diagnosis
Boolean satisfiability
electronics design automation
