摘要
介绍了一款语音压缩专用处理器的设计思路,使用嵌入式FLASH超长指令字系统有效的提高了芯片的处理能力,同时将增强型算术逻辑单元、乘法器、乘累加器结合在一起,在改进的哈佛体系结构上实现了微控制器与DSP的单核设计。使用存储器操作指示寄存器、分层寄存器组,能够简化子程序调用方式。该微处理器采用0．25μm CMOS工艺实现,芯片面积为25mm^3。仿真结果表明,在20MHz工作频率下,芯片处理能力与50MIPS的通用DSP相当,同时能够保持原有编码质量。该处理器能够实现多种类型的语音压缩算法,可以达到对语音算法的高保密性、低复杂度、易开发性。
The design idea of an application special processor, which employs embedded FI.ASH memory VLIW（very long instruction word） system to increase the chip＇s processing ability effectively, is introduced in this article. The processor also combines enhanced AI.U, multiplier and multi-accumulator to realize micro controller and DSP in a slngle core with improved Harvard architecture. The chip use memory indicating register and lever register group, which can simplify sub-program calling method. The micro processor fabricated using 0.25μm CMOS technics, and the area is 25mm^2. The simulating result shows the chip working under 20MHz has the same performance with 50MIPs general purpose DSP and maintains the original coding quality. Many types of speech compression algorithm can be implcmented on this processor and achieve to good security, low complexity and development convenience.
出处
《微计算机应用》
2006年第5期553-556,共4页
Microcomputer Applications
基金
国家自然科学基金(60572081)。
关键词
语音压缩
专用芯片
可重构体系结构
超长指令字
嵌入式处理器
speech compression, ASIC, reconfigurable architecture, very long instruction word. embedded processor
