摘要
分析特定系统通信传输的抗干扰能力,先要提取该系统在正常工作情况下的误码情况,再在此基础上对该系统的抗干扰能力进行全面分析。提出了一种基于FPGA的智能误码测试方案。先从基本组成入手,介绍误码分析仪各功能模块的作用和误码分析仪的工作过程,之后根据数字锁相环的基本原理,结合FPGA的结构特点设计了一种自适应的智能锁相的位同步法和序列同步法。
To analyze the communication performance of a certain system, BER of the system should be obtained first while in normal working conditions, based on which the anti-jammer capability of the system can be analyzed. An intellective scheme for BER testing based on FPGA is proposed. Firstly, the function of BER analyzer＇ s different modules and its working flow are presented. With the considering of the structure feature of FPGA, an adaptive and inteUective phase-locked scheme for bit and sequence synchronization is then proposed based on principle of digital phase-locked loop（ DPLL）.
出处
《测控技术》
CSCD
2006年第8期83-85,88,共4页
Measurement & Control Technology
关键词
M序列
现场可编程门阵列
位同步
序列同步
锁相
m sequence
FPGA
bit synchronization
sequence synchronization
phase-locked（PL）
