摘要
本文通过对传统大规模集成电路设计流程的优化,得到了更适合于深亚微米工艺集成电路的后端设计流程,详细介绍了包括初步综合、自定义负载线的生成、版图规划、时钟树综合、静态时序分析等,并通过前端和后端设计的相互协作对大规模集成电路进行反复优化以实现设计更优。并基于ARTISAN标准单元库,以PLL频率综合器中可编程分频器为例,在TSMC0.18μmCMOS工艺下进行了后端设计,最后给出了可编程分频器的后仿真结果、芯片照片和测试结果,芯片内核面积1360.5μm2,测试结果表明设计符合要求。
As the scale of integrated circuit enlarges and the speed increases, the back-end design in Deep Submicron （DSM） Technology has experienced a rapid development. This article, taking vider as an example, introduces the back-end design in DSM technology based on programmable the ARTISAN frequency distandard ceil. Further more, the procedure, which includes initial synthesis, timing driven placement, clock tree synthesis, static timing analysis （STA）, post-layout optimization and so on, is discussed elaborately. Finally, the layout is displayed and taped out in TSMC 0.18？m CMOS process. The test result indicates that the design complies with the requirement.
出处
《中国集成电路》
2006年第8期37-42,共6页
China lntegrated Circuit
基金
国家自然科学基金项目(60472057)资助
