摘要
根据国家信息安全领域确定的密码标准体系自行设计的对称密码算法,提出了一种高速对称密码芯片结构。芯片中加解密核心部件用流水线实现,密钥生成采用电路复用技术,兼顾了芯片的速度和面积。并提出了一种改进的二元决策电路,以实现字节替换函数,有效地减小了关键路径的时延。芯片采用中芯国际0．18μm CMOS工艺标准单元库流片成功,支持3种密钥长度和4种工作模式,可以稳定工作在80MHz,吞吐量达到2．56Gbps。
This paper introduces a high speed symmetric key data encryption/decryption IC according to the algorithm which is designed on the basis of encryption standards established by the national information security domain. In order to balance the sPeed and the area of the chip, the algorithm uses pipeline structures to realize the core and non-pipeline circuits to design the key expansion module. It also introduces the improved binary decision circuits to realize the byte substitution function so that the critical path delay is significantly reduced. The design is implemented in a 0.18μm CMOS standard cell library of SMIC and successfully fabricated. The chip, which supports three different lengths of key and four working modes, runs steadily at a maximum 80MHz, the data throughput is up to 2.56 Gbps.
出处
《计算机工程》
EI
CAS
CSCD
北大核心
2006年第14期238-240,共3页
Computer Engineering
基金
国家"863"计划基金(2003AA141040)
