摘要
通过对片外和片内高速缓冲存储器体系结构的总结与评价,着重分析了片内Cache与处理器核心部件、外部存储器之间的连接关系,并通过对于普林斯顿结构和哈佛结构的优缺点的讨论和分析可知,片内两级Cache结构中,一级Cache适用于哈佛结构,这样使得最接近处理器操作部件的Cache分开,消除数据引用和指令引用的冲突,远离操作部件的二级Cache则采用普林斯顿结构,可以动态调节指令和数据在其中的分配比例。这种综合的两级Cache体系结构,兼容了哈佛结构和普林斯顿结构的优势,弥补了二者的缺陷,充分发挥片内Cache的作用。
This paper presents the overview and evaluation of the architecture for inner and exterior Cache memory,focuses mainly on the analysis of connection relationship among the inner Cache, exterior Cache and system memory, and discusses the advantages and disadvantages of the Princeton architecture and Harvard architecture. In turn some results are achieved： for the two level Cache architecture in chip, Level 1 employs the Harvard architecture which can make the Cache nearest to the processor operation unit to be separated, and resolve the conflicting problem of data and instruction access. The other Cache, which is far away from the processor operation unit, adopts Princeton architecture that can dynamically adjust the proportion of the instruction and data in it. This integrated two level Cache architecture makes the two architectures＇advantages stronger, the disadvantage much less, and the functions of inner Cache being fully utilized.
出处
《航空计算技术》
2006年第3期29-33,共5页
Aeronautical Computing Technique
