摘要
本文提出了一种从较高的行为级描述进行ＦＰＧＡ设计，从而替代传统的以原理图作为设计输入的方法。通过高级综合，可以把用户所给出的行为功能描述自动转化为较低层次的结构描述，并进一步与ＦＰＧＡ设计系统相连完成最终设计。
he authors proposed a new methedology for FPGA design. Starting froma high-level,supported by a high-level synthesis system BITHLS,the behavioral design description is converted to the RTL structural design (a netlist). Then, based on the unit library provided by an FPGA vendor (e. g. Xilinx), the RTL netlist is mapped to the appropriate data format acceptable to the FPGA development system for constucting the real design.
出处
《计算机工程与科学》
CSCD
1996年第1期66-70,共5页
Computer Engineering & Science
