摘要
根据传统的小数分频锁相环中的采样保持方案,提出了宽带Σ-Δ锁相环中采样保持技术的实现方案.方案的采样时刻由首先出现的参考时钟信号或分频器信号的上升沿决定,可以在采样前为补偿电流和电荷泵电流提供足够的时间以保证它们在积分器上的完全积分,从而解决了使用相位内插的Σ-Δ锁相环中电荷泵电流脉冲与补偿电流脉冲间的匹配问题.仿真结果表明,使用采样保持单元后可以显著降低环路中的相位噪声和杂散噪声.
Based on the sample and hold scheme in the classic fractional-N phase-locked loop （PLL）, a novel sample and hold scheme was proposed for the wideband ∑-△ PLL. The sampling operation of the proposed topology takes place at the first coming edge of the reference clock signal and the divider signal. It can provide enough time for the charge-pump current and the compensation current to integrate completely before the sampling occurs, thus the problem of mismatch between the charge pump current pulse and the compensation current pulse in the ∑-△ PLL with phase interpolation can be eliminated. The simulation results show that the sample-and-hold element can greatly reduce phase noise and spurious noise in the loop.
出处
《上海交通大学学报》
EI
CAS
CSCD
北大核心
2006年第5期739-741,共3页
Journal of Shanghai Jiaotong University
关键词
锁相环
采样保持电路
杂散噪声
相位噪声
phase-locked loop
sample-and-hold cireuits
spurious noise
phase noise
