摘要
根据RLC互连线的二极点模型,得到一个简单的估算信号延迟和上升沿的解析表达式,并利用其实现对高速时钟电路动态优化设计,以保证信号在传输过程中不失真;同时设计了一个模拟器来验证时钟电路的性能.模拟结果表明,我们的算法降低了计算的复杂度,缩短了时钟电路优化的时间.
A simple analytical expression was obtained based on a two-pole model to evaluate the signal delay and rising time, which was then used to optimize the high speed clock circuit and to ensure signal non-distortion in transmission. Simultaneously a simulator was designed to verify the performance of the clock circuit. Simulation results show that our algorithm can reduce the computation complexity and shorten optimization time of the clock circuit.
基金
国家自然科学基金(60276042)
安徽省自然科学基金(01042104)资助
关键词
信号完整性
互连线
深亚微米
缓冲器
signal integrity
interconnect
deep sub-micrometer
buffer
