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基于适应性模拟退火的标准单元布局算法 被引量：4

Standard Cell Placement Algorithm Based on Adaptive Simulated Annealing
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摘要 提出了一种基于适应性模拟退火的标准单元布局算法,针对各布局电路的特性,在传统的模拟退火算法中引入适应性初始温度和适应性搜索区域的概念,并对标准单元布局中目标函数中的惩罚项做出相应改进。该算法用于对一组标竿电路进行测试,和传统模拟退火算法得出的结果相比,在布局效果上和时间性能上均显示出优越性。 A standard cell placement algorithm based on adaptive simulated annealing was proposed.Due to characters of all circuits to be placed, adaptively initial temperature and adaptive searching region were added to traditional simulated annealing algorithm. At the same time, punishment item in objective function was improved for standard cell placement problem. This algorithm was applied to test a set of benchmark circuits, and experiments show its advantages in placement results and time performance by comparing with traditional simulated annealing algorithm.
作者 南国芳 李敏强 寇纪淞
机构地区 天津大学系统工程研究所
出处 《系统仿真学报》 EI CAS CSCD 北大核心 2006年第3期550-553,576,共5页 Journal of System Simulation
基金 国家自然科学基金项目资助(70571057) 中国博士后科学基金资助项目(2005038151)
关键词 超大规模集成电路 标准单元 单元布局 模拟退火 VLSI standard cell cell placement simulated annealing
分类号 TP3 [自动化与计算机技术—计算机科学与技术]
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参考文献11

  • 1Bo Yao, Wenting Hou, Xianlong Hong, Yici Cai. FAME: A Fast Detailed Placement Algorithm for Standard Cell Layout Based on Mixed Min-cut and Enumeration [J]. Journal of Semiconductors,2000, 21 (8): 744-753. (In Chinese)
  • 2Terai M, Takahashi K, Sato K. A new min-cut placement algorithm for timing assurance layout design meeting net length constrain [C]//Design Automation Conference, Orlando: IEEE Computer Society,1990:96-102.
  • 3Saurabh Adya, Igor Markov, Villarrubia P G, Improving Min-cut Placement for VLSI Using Analytical Techniques [C]//IBM ACAS Conference. Austin: IEEE Computer Society Press, 2003:55-62.
  • 4Alupoaei S, Katkoori S, Net-based force-directed macrocell placement for wirelength optimization [J]. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (S 1063-8210),2002, 10( 6): 824-835.
  • 5Suit S M, Youssef H, Barada H R, AI-Yamani A, A parallel tabu search algorithm for VLSI standard-cell placement [C]// Circuits and Systems. the 2000 IEEE International Symposium on. Geneva :Press Polytechniques et Universitaries Romandes, 2000: 2: 581-584.
  • 6Manikas T W, Mickle M H, A genetic algorithm for mixed macro and standard cell placement [J]. Circuits and Systems(S1057-7130), 2002,2: 4-7.
  • 7Valenzuela C L, Wang P Y, VLSI placement and area optimization using a genetic algorithm to breed normalized postfix expressions [J].Evolutionary Computation, IEEE Transactions on, (S1089-778X),2002, 6(4): 390-401.
  • 8Aykanat C, Bultan T, Haritaoglu o, A fast neural-network algorithm for VLSI cell placement [J]. Neural Networks (S1045-9227), 1998,11: 1671-1684.
  • 9Hentschke R F, Reis R A, Improving simulated annealing placement by applying random and greedy mixed perturbations [C]//Proceedings of the 16th symposium on Integrated circuits and systems design,Washington: IEEE Computer Society, 2003:267 - 272.
  • 10Lihong Zhang, Kleine U, A genetic approach to analog module placement with simulated annealing [J]. Circuits and Systems(S1057-7130), 2002, 1: 345-348.

同被引文献44

  • 1陆承宇,章文立.CIM电网模型的拓扑分析方法[J].浙江电力,2005,24(4):5-8. 被引量：12
  • 2徐宁,杨程.混合模拟退火算法解决VLSI布局问题[J].微电子学与计算机,2006,23(10):51-53. 被引量：5
  • 3刘红,韦穗.基于遗传算法的布局问题求解[J].计算机技术与发展,2007,17(1):74-75. 被引量：3
  • 4Hou Wenting, Yu Hong, Hong Xianlong, et al. A New Congestion-driven Placement Algorithm Based on Cell Inflation[J]. Chinese Journal of Semiconductors, 2001, 22(3): 275-285.
  • 5Sechen C. Efficient and Effective Placement for Very Large Circuits[J]. IEEE Trans. on Computer-Aided Design, 1995, 14(3): 349-350.
  • 6Moon B R. Dynamic Embedding for Genetic VLSI Circuit Portioning[J]. Engineering Applications of Artificial Intelligence, 1998, 3(5): 67-76.
  • 7Cohoon J .P. Genetic Placement[J]. IEEE Trans. on Computer-Aided Design, 1987, 6(6): 956-964.
  • 8Manikas, Mickle M H. A genetic algorithm for mixed macro and standard call placement[J]. Circuits and Systems, 2002(2) :4 -7.
  • 9Aykanat C, Bultan T, Haritaoglu O. A fast neural- network algorithm for VLSI cell placement [J ]. Neural Networks, 1998(11):1671- 1684.
  • 10Hentschke R F, Reis R A. Improving simulated annealing placement by applying random and greedy mixed perturbations[C]// Proceedings of the 16th symposium on Inte- grated circuits and systems design. Washington: IEEE Computer Society, 2003 : 267 - 272.

引证文献4

二级引证文献33

系统仿真学报
2006年 第3期

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