摘要
本文针对SOC测试数据压缩,提出了一种新的可挑选变长输入编码(SVIC)方案。先采用一启发式的贪婪算法, 得到带有无关位测试集TD的差分矢量序列Tdiff后,再用该SVIC编码对其进行压缩,以缩短测试时间,降低测试数据带宽的要求。文中同时给出了相应SVIC解码器的设计。实验结果表明,在硬件开销接近时,SVIC的压缩比可比SC编码平均高出约 17.46%;而与VIHC编码相比,虽然其压缩比略有下降,但SVIC解码器所要求的面积开销却可显著降低。
The paper proposed a new Selected Variable-length Input Coding（SVIC） for System on Chip （SOC） test data compression. A heuristic greedy algorithm is used to get the difference vector sequences Tdiff from test vector sets TD with unspecified bits. Then Tdiff is compressed with SVIC to shorten test time and lower the requirement for test data bandwidth. In the meantime, the corresponding design of SVIC decoder is given. Experimental results showed that the compression ratio（CR） of SVIC is averagely higher 17.46% than that of SC under the condition of approximate hardware overhead. Although CR of SVIC is less slightly than that of VIHC, the area overhead of SVIC decoder required may be reduced significantly.
出处
《电子测量与仪器学报》
CSCD
2006年第1期73-78,共6页
Journal of Electronic Measurement and Instrumentation
基金
国家自然科学基金资助(编号:90407007)西华大学人才基金资助
关键词
SOC测试
数据压缩
SVIC编码
解压结构
SOC test, data compression, SVIC coding, decompression architecture.
