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一种3.8 GHz 0.25 μm CMOS低噪声放大器的设计 被引量：3

Design of a 3.8GHz 0.25μm CMOS Low Noise Amplifier
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摘要 从优化电路结构出发,提出并设计了一种工作于3.8 GHz的低噪声放大器。与传统级联结构相比,该电路引入了级间匹配网络。级间匹配网络的实现,可以使整个电路的功率增益、噪声系数等关键性能指标得到改善。电路采用0.25μm RF CMOS工艺制作,用Hspice软件对电路进行了模拟。结果表明,该电路的正向功率增益为15.67 dB,NF为2.88 dB,IIP3为-0.21 dBm,功耗为25.79 mW。 A 3.8 GHz low noise amplifier （I.NA） is designed, into which an inter-stage matching network is in troduced, compared with the traditional cascaded structure. The reallzation of the inter stage matching network can improve the performance of key parameters, such as power gain and noise figure. This circuit is implemented in a 0. 25 μm RF CMOS technology and simulated with Hspice. Results from simulation show that the circuit has a forward power gain of 15.67 dB, a noise figure of 2.88 dB, an IIP3 of 0.21 dBm, and a power dissipation of 25.79 mW.
作者 王磊 余宁梅
机构地区 西安理工大学电子工程系
出处 《微电子学》 CAS CSCD 北大核心 2006年第1期101-104,共4页 Microelectronics
基金 日本OKI公司资助项目
关键词 CMOS 低噪声放大器 级间匹配网络 片上螺旋电感 噪声系数 CMOS Low noise amplifier Inter-stage matching network On-chip spiral inductor Noise figure
分类号 TN722.3 [电子电信—电路与系统]
  • 相关文献

参考文献10

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共引文献5

同被引文献21

  • 1樊华,冯全源.一种超低功耗放大器的设计[J].微电子学,2005,35(6):677-679. 被引量：1
  • 2肖珺,李永明,王志华.低功耗CMOS低噪声放大器的设计[J].微电子学,2006,36(5):670-673. 被引量：12
  • 3R Jacob Baker.CMOS电路设计·布局与仿真[M].陈中建,译.北京:机械工业出版社,2006.
  • 4Mohamed El-Nozahi,Edgar Sanchez-Sinenci and Kamran Entesari.A CMOS Low-Noise Amplifier With Reconfigurable Input Matching Network [J]. IEEE Trans Microwave Theo and Tech,2009,57(5):1054 1062.
  • 5Nguyen T K,Kim C H, Ihm G -J. etal. CMOS Low Noise Amplifier Design Optimization Techniques[J ]. IEEE Trans Microwave Theo and Tech,2004,52(5) : 1433-1442.
  • 6Chieh-Pin Chang,Ja-Hao Chen,and Yeong Her Wang. A Fully Integrated 5 GHz Low Voltage LNA Using Forward Body Bias Technology[J]. IEEE Microwave. and Wireless Components Letters, 2009,19 (3): 176-178.
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  • 10刘长军,黄卡玛,闫丽萍.射频通信电路设计[M].北京:科学出版社,2008.269-270.

引证文献3

二级引证文献9

微电子学
2006年 第1期

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