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集成注入邏辑电路中的最小延迟时间

Minimum Delay Time of the Integrated Injection Logic Gate
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摘要 用模拟和电荷控制原理,对集成注入逻辑的最小延迟时间进行分析,分析表明:要实现开关的高速工作,必须将存储电荷减至最小,对基区进行高浓度P^+扩散能使存储电荷减少。最后提出要进一步改进开关速度还应使基本门的版图尺寸尽可能小,使比值Sc/S_L保持不变。 How fast the integrated injection logic gate can operate is one of the most interesting problems which integrated injection logic designers are concerned with. In this paper, two-dimensional simulation and the charge control principles have been applied to analyze the speed of the integrated injection logic gate. It has been revealed that, for the improvement of the switching speed, the amount of the stored charge should be minimized, and the geometry of the gate should be made as small as possiple, keeping the ratio S_C/S_L constant to prevent β_u degradation.
作者 孙崇德
出处 《暨南大学学报(自然科学与医学版)》 CAS CSCD 1989年第3期43-47,51,共6页 Journal of Jinan University(Natural Science & Medicine Edition)
关键词 逻辑电路 集成注入 延迟时间 Two-Dimensional simulation, Stream function, Quasi-Fermi potential
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