摘要
边缘扫描测试是对大规模集成电路（ＶＬＳＩ）进行测试的一种新的基于可测性设计的测试技术，能极大地降低ＶＬＳＩ测试生成的复杂性，在电路设计与测试领域，近年来得到广泛关注。本文讨论了这种测试技术的产生背景，实现方法，及与常规方法相比存在的优势，并就其今后的发展将解决的问题作了研究。
Boundary scan testing based on design-for-testability is a new method to test VLSI.This method can greatly reduce the complexity of VLSI test generation,so it has been studied extensively in the fields of design and test of integrated circuit in recent years. The design ideas, main features, implementation techniques of the method are discussed in this paer. The advantages of the method over the conventional approaches are analysed in detail and the problem to be solved is also discussed.
出处
《系统工程与电子技术》
EI
CSCD
1996年第2期9-14,共6页
Systems Engineering and Electronics
基金
国家"八五"攻关基金
关键词
集成电路
测试
边缘扫描测试
VLSI
Integrated circuit, Design for testability, Computer aided test, Boundary scan testing.
