摘要
在SAR图像中检测舰船本身或其尾迹时,往往运算量非常大,为了满足未来业务化操作中高速和实时性的要求,本文提出了一种基于FPGA的硬件实现方法,提出了应用VHDL在ALTERAStratixIIep2s30芯片上实现检测中复杂的并行运算。内容包括软件仿真和硬件实现。
In this paper, we describe a novel FPGA-based architecture for the detection algorithms of moving ships in SAR images. We introduce the approach using flatness and the dissymmetry characteristics of the distribution shape and introduce its implementation because of the speed requirement. The proposed architecture consists of software simulation and hardware implementation. The hardware is implemented on Altera StratixⅡ ep2s30 FPGA using VHDL.
出处
《微计算机信息》
北大核心
2005年第11Z期119-121,共3页
Control & Automation
基金
国防科技重点实验室基金项目支持项目编号:51444060105ZK1301
