摘要
为满足现代高分辨率雷达大容量高速缓存以及被动雷达和时差定位系统采样预触发的需要,提出了采用多片先进先出(F IFO)芯片级联的硬件结构实现可编程采样预触发和缓存容量扩展.分析了两级F IFO级联时芯片间接口的时序,给出了对F IFO可编程标志位的设置方法.实际应用证明,采用该结构可使系统的缓存容量达到2 M B,预触发量达到1 M B,且两种功能可由FPGA控制切换.该结构也适用于其它具有可编程标志的F IFO.
To satisfy high speed large capacity of data buffering in modern high-resolution radar and pre-triggering sampling in passive radar or passive time-of-arrival-location （TOA） system, the article presents an architecture to expand the buffering capacity and realize pre-triggering function using multi-first input first output （FIFO） in series, analyzes the timing between two level FIFOs, and presents a method for setting the programmable flag in FIFO. Practice demonstrates that, the capacity of buffering amounts to 2 MB, and the number of pre-triggering amounts to 1 MB. Further more, the functions can be switched by FPGA. The configuration is also fit for other kinds of FIFO having programmable flag.
出处
《北京理工大学学报》
EI
CAS
CSCD
北大核心
2005年第11期985-988,共4页
Transactions of Beijing Institute of Technology
基金
国家部委预研项目(51407030404BQ0107)
关键词
先进先出存储器
存储容量扩展
采样预触发
可编程标志
first input first output（FIFO）
expanding storage depth
pre-trigger
programmable flag
