摘要
考虑到QoS需求以及带宽的有效利用,高速有效的调度算法成为当前路由器中研究的热点。DRR算法具有较低的设计复杂度以及适应变长分组交换的特点,使之便于在T-Bit路由器中实现。文中介绍了设计的主要模块以及具体的硬件实现方案。
A need arises for scheduling packets in a network when one takes into account different Quality of Service issues and efficient use of available bandwidth. DRR arithmetic has low design complexity and adopt packet switching with different packet sizes. Our final project implements Deficit Round Robin Scheduling running on an FPGA inside a T-bit switch. This paper describes the major components involved in the design and how they were implemented in hardware.
出处
《微计算机信息》
北大核心
2005年第08Z期100-101,6,共3页
Control & Automation
基金
国家"863"项目(2001AA121011)
